In the field of semiconductor manufacturing, with the development of the integration and miniaturization of semiconductor devices, the size of shallow trench isolation structures (STI) used to electrically isolate adjacent semiconductor devices correspondingly becomes smaller. However, the STI structure is often made of silicon oxide which is different from the material of a semiconductor substrate, when the STI structure is used to isolate the adjacent semiconductor devices, a stress effect can be induced to the surrounding semiconductor substrate, and affect the electrical properties of a MOS transistor.
FIG. 1 shows a cross-section view of an existing MOS transistor with an STI structure. As shown in FIG. 1, the existing MOS transistor with an STI structure includes: a semiconductor substrate 10, an active region 11 in the semiconductor substrate 10, a gate structure 12 on the active region 11, a drain region 13 and a source region 14 at both sides of the gate structure 12, a channel region 15 underneath the gate structure 12 and an STI structure 18 in the semiconductor substrate 10 and around the MOS transistor. The STI structure 18 isolates adjacent MOS transistors. Because the STI structure 18 is formed by a high temperature chemical vapor deposition process (CVD), the temperature of forming silicon dioxide in the shallow trench is very high. When the silicon dioxide is cooled down from a deposition temperature to the room temperature after the CVD process, both silicon dioxide and the silicon semiconductor substrate may shrink. Because the thermal expansion coefficients of silicon and silicon dioxide are different, the shrink amount of silicon and silicon dioxide would be different. Correspondingly, STI structure will generate a considerable stress to channel region 15, which is highly dependent on the STI formation process.
FIG. 2 shows existing multiple MOS transistors with an STI structure 28, in which seven PMOS transistors are surrounded by the STI structure 28. Source region and drain region 24 of a PMOS transistor are made of silicon germanium. Thus, a channel region 25 would have a compressive stress caused by lattice mismatch between silicon and silicon germanium. FIG. 3 is a lateral stress distribution of the multiple channel regions 25, source/drain regions 24 of the seven PMOS transistors surrounded by the STI structure 28 shown in FIG. 2. It may be shown that the seven channel regions 25 undergo compressive stress, and the compressive stress of the channel regions of the PMOS transistors proximity to the STI structure 28 is 24%˜35% smaller than the compressive stress of the channel regions of the PMOS transistors far from the STI structure 28 due to STI stress impact. It may cause additional electrical property variation of MOS to MOS transistors.
Further, with the shrinking of the size of semiconductor devices, the Aspect Ratio (AR) of the STI structure is increasing. In order to make silicon dioxide to completely fill the shallow trench without voids, utilizing a High Aspect Ratio Process (HARP) to form STI structures becomes more and more common. However, the STI structure further generates tensile stress to the surrounding semiconductor substrate when the—High Aspect Ratio process (HARP) is used to form the STI structure.
Currently, the impact of tensile stress of the STI structure may be alleviated by creating dummy gate close to STI structures or optimizing the integration process and scheme of the STI modules, but these approaches often need extra steps and introduce side-effects. Thus, it may make the fabrication process become more complex, and increase the production cost at the same time. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.